The invention relates to the general field of semiconductor devices, and in particular to a field implant used to adjust operating characteristics of an SCR in an electrostatic discharge protection circuit.
High voltage electrostatic discharge (ESD) can damage fied effect transistor (FET) devices. Various combinations of diodes, transistors and resistors have been suggested to clamp electrostatic voltage excursions to levels below the gate oxide breakdown limits. A technique for reducing susceptibility to latchup is to form the FET devices in an epitaxial layer above a low impedance substrate. Additionally, guard rings and retrograde well dopant concentrations are known.